1. Field of the Invention
The present invention relates to a voltage regulator with a reduced influence of an offset.
2. Description of the Related Art
FIG. 2 is a circuit diagram illustrating a conventional amplifier circuit.
In the conventional amplifier circuit, a drain of a normal breakdown voltage NMOS transistor 301 and a source of a high breakdown voltage NMOS transistor 302 are connected to each other, and a drain of the high breakdown voltage NMOS transistor 302 is connected to an output terminal 311. In this manner, a high load impedance can be set to obtain a large output voltage swing, and hence the gain of the amplifier circuit as a whole can be increased (see, for example, Japanese Patent Application Laid-open No. 2005-311689).
In a conventional voltage regulator, however, if an amplifier is formed by a cascode amplifier circuit using a high breakdown voltage MOS transistor, an offset is generated in the first stage amplifier.